The Design of High Performance Asynchronous Pipelines with Quasi Delay-Insensitive
نویسندگان
چکیده
منابع مشابه
The Design of High Performance Asynchronous Pipelines with Quasi Delay Insensitive
VLSI Design looking towards to solve design constructions that arises when using clock pulses. The majority of the constrains can be overcome by using asynchronous logic, additionally synchronous circuits has some inherent advantages over synchronous counterparts. This paper demonstrates the design of efficient asynchronous pipelines for some standard logic circuits and medium scale integration...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2012
ISSN: 0975-8887
DOI: 10.5120/8289-1862